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Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
FEATURES
* Common parallel I/O for reduced pin count * Additional serial inputs and outputs for expansion * Four operating modes: Shift left, shift right, load, and store * 3-State outputs for bus-oriented applications
DESCRIPTION
The 74F323 is an 8-bit universal shift/storage register with 3-State outputs. Its function is similar to the 74F299 with the exception of synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin counts. Separate serial inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. Four modes of operation are possible: Hold (store), shift left, shift right, and parallel load. The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load, and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A Low signal on SR overrides the Select and inputs and allows the flip-flops to be reset by the next rising edge of clock. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed. A High signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation.
PIN CONFIGURATION
S0 OE0 OE1 I/O6 I/O4 I/O2 I/O0 Q0 SR 1 2 3 4 5 6 7 8 9 20 VCC 19 S1 18 DS7 17 Q7 16 I/O7 15 I/O5 14 I/O3 13 I/O1 12 CP 11 DS0
GND 10
SF00888
TYPE 74F323
TYPICAL fMAX 115MHz
TYPICAL SUPPLY CURRENT (TOTAL) 55mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F323N N74F323D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DS0 DS7 S0, S1 CP SR OE0, OE1 Q0, Q7 I/On Serial data input for right shift Serial data input for left shift Mode select inputs Clock pulse input (Active rising edge) Synchronous Reset input (Active Low) Output Enable input (Active Low) Serial outputs Multiplexed parallel data inputs or DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 3.5/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.2mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/20mA 70A/0.6mA 3.0mA/24mA
3-State parallel outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High State and 0.6mA in the Low state.
1990 Mar 01
1
853-0367 98987
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
LOGIC SYMBOL
11 18
LOGIC SYMBOL (IEEE/IEC)
SRG8 9 2 DS0 DS7 3 1 19 12 11 7 0 1 4R & 3EN13 M 0 3
1 19 12 9 2 3
S0 S1 CP SR OE0 OE1 Q0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
C4/1 /2 1, 4D 3, 4D 5, 13 Z5 Z6 8
13
3, 4D 6, 13
6 VCC = Pin 20 GND = Pin 10 8 7 13 6 14 5 15 4 16 17 14 5 15 4 16 18 3, 4D 12, 13 2, 4D Z12 17
SF00889
SF00890
FUNCTION TABLE
INPUTS OEn L L L L L H H L X = = = = SR L H H H H X S1 X H L H L X S0 X H H L L X CP X X OPERATING MODE Synchronous Reset; Q0 - Q7 = Low Parallel load; I/On Qn Shift right; DS0 Q0, Q0 Q1, etc. Shift left; DS7 Q7, Q7 Q6, etc. Hold Outputs disabled (3-state)
High voltage level Low voltage level Don't care Low-to-High clock transition
1990 Mar 01
2
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
LOGIC DIAGRAM
DS7 18 OE0 OE1 19 2 3 CP D S1 Q 16 I/O7 17 Q7
S0 SR
1 9 CP D Q 4 I/O6
CP D Q 15 I/O5
CP D Q 5 I/O4
CP D Q 14 I/O3
CP D Q 6 I/O2
CP D Q 13 I/O1
CP D 11 12 8 Q0 Q 7 I/O0
DS0 CP VCC = Pin 20 GND = Pin 10
SF00883
1990 Mar 01
3
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature Q0, Q7 I/On PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +5.5 40 48 0 to +70 -65 to +150 UNIT V V mA V mA mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Q0, Q7 I/On Low-level output current Operating free-air temperature range Q0, Q7 I/On 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 -3 20 24 70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA mA mA C UNIT
IOL Tamb
1990 Mar 01
4
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.5 2.7 2.5 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 1 20 -1.2 -0.6 70 3.4 TYP2 MAX UNIT V V V V V V V A mA A mA mA A mA mA mA mA
Q0, Q7 VOH High-level output voltage I/On
VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN
IOH = -1mA
IOH = -3mA
VOL VIK II IIH IIL
Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current Low-level voltage applied Short-circuit output current3 ICCH others I/On except I/On S0, S1 others
IOL = MAX
VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = 5.5V, VI = 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V
IIH + IOZH IIL + IOZL IOS ICC
I/On only
VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX -60 55 VCC = MAX 65
-0.6 -150 75 90
Supply current (total)
ICCL
ICCZ 55 85 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb =+ 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1990 Mar 01
5
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Q0 or Q7 Propagation delay CP to I/On Output Enable time Sn, OE to I/On Output Disable time Sn, OE to I/On I/O Qn Waveform 1 Waveform 1 Waveform 3 Waveform 4 Waveform 3 Waveform 4 Waveform 1 70 85 4.0 3.5 4.0 5.0 3.5 4.0 2.5 1.5 TYP 100 115 6.0 6.0 6.0 6.5 6.0 8.0 5.0 3.0 8.5 8.5 9.0 9.5 9.0 11.0 7.5 5.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 70 85 3.5 4.5 4.0 4.0 3.5 4.0 2.5 1.5 9.5 9.5 10.0 10.0 10.0 11.5 8.0 6.5 MAX MHz MHz ns ns ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low S0 or S1 to CP Hold time, High or Low S0 or S1 to CP Setup time, High or Low I/O0, DS0 or DS7 to CP Hold time, High or Low I/O0, DS0 or DS7 to CP Setup time, High or Low SR to CP Hold time, High or Low SR to CP CP Pulse width, High or Low Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 1 6.5 6.5 0 0 3.5 3.5 0 0 7.0 7.0 0 0 3.5 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 7.5 7.5 0 0 4.0 4.0 0 0 8.5 8.5 0 0 4.0 4.0 MAX ns ns ns ns ns ns ns UNIT
1990 Mar 01
6
Philips Semiconductors
Product specification
8-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
74F323
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX CP S0, S1, DSL, DSR, I/On, SR VM tW(L) tPLH VM VM CP
VM ts(H) VM
VM th(H)
VM ts(L)
VM th(L) VM
VM tW(H) tPHL
Q0, Q7, I/On
SF00885
Waveform 2. Data, Select and Reset Setup and Hold Times
SF00884
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Sn, OEn
VM tPZH
VM tPHZ VM 0V VOH -0.3V
Sn, OEn
VM tPZL
VM tPLZ VM VOL +0.3V
I/On
I/On
SF00886
SF00887
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1990 Mar 01
7

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